An electronic circuit may contain many electronic circuit components, e.g., thousands or even millions of individual resistors, capacitors, inductors, diodes, and transistors. These individual circuit components must be interconnected to form the circuits, and the individual circuits must be interconnected to form functional units. Power and signal distribution are done through these interconnections. The individual functional units require mechanical support and structural protection. The electrical circuits require electrical energy to function, and the removal of thermal energy to remain functional. Microelectronic packages, for example, chips, modules, circuit cards, and circuit boards, are used to protect, house, cool, and interconnect circuit components and circuits.
Within an integrated circuit, circuit component to circuit component and circuit to circuit interconnection, heat dissipation, and mechanical protection are provided by an integrated circuit chip. This chip enclosed within its module is referred to as the first level of packaging.
There is at least one further level of packaging. This second level of packaging is the circuit card. The circuit card is necessary for at least three functions. First, the circuit card is employed because the total required circuit or bit count to perform a desired function exceeds the bit count of the first level package, i.e., the chip. Second, the second level package, i.e., the circuit card, provides a site for components that are not readily integrated into the first level package, i.e., the chip or module. These components include, e.g., capacitors, precision resistors, inductors, electromechanical switches, optical couplers, and the like. Third, the circuit card provides for signal interconnection with other circuit elements.
In most applications there is a third level of packaging. This is the board level package. The board contains connectors to accept a plurality of cards.
Package design, that is, card and board design, have been driven by the necessity of accommodating an ever increasing density of interconnections in a small area. In order to accommodate this higher density of interconnections, cards and boards have multilayer structures.
Cards and boards, while used in both digital and analog circuits, find their greatest application in digital circuits. In digital circuits a narrow band around one discrete value of voltage corresponds to a logical "0" and another narrow band around a second discrete value of voltage corresponds to a logical "1." Signals having these properties are "digital signals." Digital information processing depends upon the transmission, storage, and application of these digital signals.
In digital information processing, a signal changes from one binary level to another. This change is ideally transmitted as a "step function." However, this ideal step function becomes distorted because of resistance, capacitance, inductance, and transmission line effects in the transmission line and in other transmission lines in the package. Moreover, this step function, whether ideal or distorted, gives rise to still other distortions and spurious signals, i.e., noise, and induced signals on other lines in the circuit package. Thus, it is necessary to filter noise out of digital circuits.
Filtering may be accomplished in digital circuit packages by providing internal RC filter circuits of appropriate RC time constant and band pass characteristics, and thereby capacitively coupling, or decoupling, signal lines with, for example, power lines, ground lines, or other signal lines.
Attempts at providing internal capacitance and RC circuits to accomplish these ends are well known in the art. For example, U.S. Invention Registration H416, of Kevin W. Colvin, for HIGH CAPACITANCE FLEXIBLE CIRCUIT, published Jan. 5, 1988, describes a multilayer flexible circuit having discrete ceramic capacitors embedded therein. In the circuit package of Colvin the capacitive elements are comprised of chips or wafers of a material different from the flexible substrate, and having a high dielectric constant, with the opposite surfaces of each such chip having a conductive coating.
U.S. Pat. No. 4,682,414 to Sheldon H. Butt for MULTILAYER CIRCUITRY describes a multilayer circuit package having a recess on one surface. As described by Butt, one discrete electronic element is positioned within the recess, while a second discrete electronic element is positioned on the surface of the package.
U.S. Pat. No. 4,705,917 to Louis E. Gates et al. for MICROELECTRONIC PACKAGE describes a microelectronic package having interior openings to provides recesses in which chips and discrete capacitors can be located and connected. Specifically, Gates et al. describe a microelectronic package formed of a plurality of layers of ceramic, with some of the layers having openings in the interior thereof. These internal openings form recesses within the package to carry discrete components. Disclosed discrete components include capacitors.
U.S. Pat. No. 4,729,061 to Candice Brown for CHIP ON BOARD PACKAGE FOR INTEGRATED CIRCUIT DEVICES USING PRINTED CIRCUIT BOARDS AND MEANS FOR CONVEYING THE HEAT TO THE OPPOSITE SIDE OF THE PACKAGE FROM THE CHIP MOUNTING SIDE TO PERMIT THE THE HEAT TO DISSIPATE THEREFROM discloses a circuit package having at least one cavity for mounting an integrated circuit die therein.
U.S. Pat. No. 4,751,126 to Hirosi Oodaira et al. for A METHOD OF MAKING A CIRCUIT BOARD AND A CIRCUIT BOARD PRODUCED THEREBY discloses a flexible circuit package in which flexible substrates are bonded together. Oodaira specifically discloses that a discrete circuit element, such as a capacitor, may be buried between the flexible substrates, utilizing the plastic deformation of the flexible substrate.
U.S. Pat. No. 4,744,008 to Vincent J. Black et al. for FLEXIBLE FILM CHIP CARRIER WITH DECOUPLING CAPACITORS describes a microelectronic package formed of a circuitized polyimide film chip carrier with at least one discrete decoupling capacitor mounted on a surface thereof.
U.S. Pat. No. 4,460,938 to Alain Clei for PROCESS FOR PRODUCING HYBRID CIRCUITS WITH INTEGRATED CAPACITORS AND RESISTORS AND CIRCUITS OBTAINED BY THIS PROCESS describes a hybrid circuit structure, i.e., not a circuit package as such, with thin film capacitors having a valve metal, e.g., tantalum, electrode, and a dielectric of a native oxide of tantalum. The native oxide is formed by anodizing, i.e., oxidizing, the tantalum.
U.S. Pat. No. 4,328,520 to Christopher H. Bajorek et al. for MULTIPLE LAYER, CERAMIC CARRIER FOR HIGH SWITCHING SPEED VLSI CHIPS describes a microelectronic package carrying thin capacitor sheets laminated in a ceramic structure. The capacitor electrode plates may serve as the power distribution conductors (power planes). Alternatively, the electrode plates may be connected to power conducting vias which pass to or through the power planes. The capacitive elements are laminates of thin metallic sheets and dielectric material. The capacitive laminates are formed by successively forming a green (unfired) sheet of the green (unfired) dielectric and the metallic conductor layer thereon to a desired number of layer pairs, firing the green (unfired) laminate to form the capacitive laminate, and circuitizing external surfaces thereof.
According to an alternative exemplification of Bajorek et al. the capacitive laminate is formed by metallizing green (unfired) sheets, sintering the individual metallized green (unfired) sheets, and joining the individual, metallized and fired laminates together, for example with glass and brazing materials, and metallizing the top surface thereof.
U.S. Pat. No. 4,237,522 to David A. Thompson for CHIP PACKAGE WITH HIGH CAPACITANCE, STACKED VLSI/POWER SHEETS EXTENDING THROUGH SLOTS IN SUBSTRATE describes the use of capacitively coupled, insulated power sheets for connecting power from the bus lines to the chips. The insulated power sheets are a thick film laminate of 10 mil thick conductor and 0.5 mil thick dielectric layers.
U.S. Pat. No. 3,949,275 to Wolf-Dieter Muenz for ELECTRIC THIN FILM CIRCUIT AND METHOD FOR ITS MANUFACTURE discloses a thin film circuit having a thin film capacitor with a dielectric layer between a pair of electrodes, where the dielectric is a native oxide of the material used to form the electrode. The electrode is formed of a valve metal, and the native oxide dielectric layer is formed by oxidation, i.e., anodization, of a surface of the electrode material.
U.S. Pat. No. 3,699,011 to Takeo Nishimura for METHOD OF PRODUCING THIN FILM INTEGRATED CIRCUITS discloses a thin film circuit with a thin film capacitor immediately subjacent a semiconductor. The thin film capacitor has a dielectric layer between a pair of electrodes, with the dielectric being a native oxide of the material used to form the electrode. The electrode is formed of an oxidizable metal, e.g., a valve metal, and the native oxide dielectric layer is formed by oxidation, i.e., anodization, of a surface of the electrode material.
U.S. Pat. No. 3,665,346 to William Orr for THIN FILM DISTRIBUTED RC STRUCTURE, a division of U.S. Pat. No. 3,542,654, discloses a thin film RC circuit component on an inert substrate, and consisting of the inert substrate, an anodizable resistive film, an oxide dielectric produced on the anodizable film, and a conductive counter electrode produced on the opposite surface of the dielectric film. The resistive film is a refractory metal that is readily anodized to form a dielectric native oxide.
Laid Open European Patent Application No. 0-083-405 of Dudley A. Chance et al for CHIP CARRIER FOR LARGE SCALE INTEGRATED CIRCUITS AND A METHOD FOR THE FABRICATION OF THE CARRIER, corresponding to U.S. Pat. No. 4,453,176, for LSI CHIP CARRIER WITH BURIED REPAIRABLE CAPACITOR WITH LOW INDUCTANCE LEADS discloses a carrier for LSI chips including a buried capacitor structure. While the exact method of fabricating the capacitor structure is not disclosed, at least one electrode layer of the capacitor structure comprises a plurality of segmented electrode plates. Each of the individual electrode plate segments are individually addressable through individual via lines which extend from the internal electrode segment to severable links on the chip mounting surface of the carrier. The individual severable links can be cut, e.g., by a laser, to repair or delete a defective segment of the capacitor.
Still other buried capacitor structures are shown, for example, in:
a. Japanese Patent Application No. 59-233109, filed Nov. 7, 1984 in the name of Hitachi Ltd. for SEMICONDUCTOR DEVICE, and laid open as Kokai 61-112369 on May 30, 1986. This application describes a capacitor deposited on the external surface of a chip carrier. The capacitor is deposited atop a passivating layer, and includes (i) an aluminum ground layer, (ii) a dielectric layer, exemplified by a silicon nitride layer, (iii) an aluminum power source layer, and (iv) an SiO.sub.2 insulating layer.
b. Japanese Patent Application No. 59-127869, filed June 21, 1984 in the name of Nippon Denki K.K. for PLUG-IN PACKAGE WITH CAPACITOR, and laid open as Kokai No. 61-6846 on Jan. 13, 1986. This application describes the use of a discrete internal capacitor chip to filter the power supply to a chip mounted on the package.
c. Japanese Patent Application No. 57-192963 filed Nov. 11, 1982 in the name of Matsushita Denshi Kogyo K.K. for PACKAGE FOR SEMICONDUCTOR DEVICE, and laid open as Kokai No. 59-82753 on May 12, 1984, discloses a microelectronic package where the capacitor is structurally and electrically between an embedded memory chip and the ground plane of the package.
d. Japanese Patent Application 57-164460 filed Sept. 21, 1982 in the name of Nippon Denki K.K. for SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, and laid open as Kokai 59-54254 on Mar. 29, 1984, discloses a microelectronic package where a resin embedded capacitor is structurally and electrically between a memory chip and the power supply plane of the package.
e. Japanese Patent Application 57-115045 filed June 30, 1982 in the name of Mitsubishi Denki K.K. for SEMICONDUCTOR DEVICE, and laid open as Kokai 59-5654 on Jan. 12, 1984, discloses a capacitor that may be either within a flip chip substrate or on the surface of the flip chip. The capacitor is in parallel with the power supply to the chip.
J. M. Brownlow, STRESS AVOIDANCE IN COFIRED TWO MATERIAL CERAMICS, IBM Technical Disclosure Bulletin, Vol. 22, (9) (February 1980), pages 4256-4257 describes the problems arising from the mismatch of coefficients of thermal expansion between the structural ceramic material used in fabricating the package, and the high capacitance ceramics used for relatively thick internal capacitors. Brownlow describes the problem of high stress and cracking occurring when structural ceramic layers are allowed to sinter to titanate high capacitance dielectrics. Brownlow discloses one solution to this problem, where the capacitor, i.e., the titanate and its electrodes, are formed by first forming a resin-ceramic, e.g., from a slurry of resin and ceramic, and thereafter screening a resin-metal pattern onto the resin-ceramic sheets. A resin rich paste is used to mechanically isolate the capacitor from the monolithic package structure, thereby preventing thermal stresses.
R. O. Lussow, INTERNAL CAPACITORS AND RESISTORS FOR MULTILAYER CERAMIC MODULES, IBM Technical Disclosure Bulletin, Vol. 20, (9) (February 1978), pages 3436-3437, discloses forming buried internal capacitors by depositing green (unfired) dielectric pastes in appropriately located vias, and firing the green (unfired) package to form capacitive elements.
C. H. Bajorek, D,A, Chance, C. W. Ho, and E. E. Shapiro, INTEGRATED, LOW INDUCTANCE, SMALL AREA CAPACITORS FOR VLSI SEMICONDUCTOR PACKAGES, IBM Technical Disclosure Bulletin, Vol. 25, (2) (July 1982), pages 883-888 describes a low inductance parallel plate capacitor structure for electronic packages. The parallel plate capacitor is illustrated as being part of a multi-layer ceramic interposer in FIGS. 2A and 2D of the paper, and as being flush mounted within a pocketed package immediately subjacent the semiconductor chips in FIGS. 2B and 2C of the paper.
As seen above, the art teaches various methods of and structures for providing capacitance in microelectronic packages. These include buried thick film capacitors, surface mounted capacitors, surface film capacitors, and discrete capacitors within various recesses, inserts, and hollows. The mounting of discrete capacitors within the circuit package requires extra fabrication steps. Moreover, the use of discrete capacitors gives rise to inflexiblity in providing specific RC time constants, pass band widths, capacitive coupling, and capacitive decoupling.
The use of thick film methodologies, i.e., successive laminating and sintering of interleaved layers of green (unfired) dielectric and metallic conductor, is not an altogether satisfactory solution. Multilevel vias are required. There is minimal design control of the capacitor parameters, dielectric thickness and electrode area. Moreover, thick film hetero-structures within the package introduce thermal expansion mismatches into structural package members.
Thus, a clear need exists for a simple package fabrication method that provides the ability to obtain specific values of package capacitance, while preserving the structural, thermal, and electrical integrity of the package.